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Freescale Semiconductor /MK70F15WS /DDR /CR57

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Interpret as CR57

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CMDDLY0RESERVED 0CLKDISDLY 0RESERVED0CLKENDLY 0RESERVED 0 (0)ODTALTEN 0RESERVED

ODTALTEN=0

Description

DDR Control Register 57

Fields

CMDDLY

Command Delay
RESERVED

Reserved
CLKDISDLY

DFI Clock Disable Delay
RESERVED

Reserved
CLKENDLY

DFI Clock Enable Delay
RESERVED

Reserved
ODTALTEN

ODT Alternate Enable

0 (0): Disable

1 (1): Enable
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data